A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash, memory cell includes a source, drain, and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The flash memory cell provides for nonvolatile data storage.
A typical configuration of an array of flash memory cells includes rows and columns of flash memory cells. The array is supported by word lines and bit lines, wherein the word lines are coupled to gates of flash memory cells, and the bit lines are coupled to drains.
In a dual bit flash memory cell, the flash memory cell stores data by holding charge within an oxide-nitride-oxide (ONO) layer. The charge storage element within the ONO layer allows electrons to be stored on either side of the flash memory cell. As a result, the basic memory cell behaves as two independent conventional memory cells. In a typical dual bit flash memory cell, a program operation is done by injecting hot electrons into the ONO layer, and an erase operation is done by injecting hot holes into the ONO layer.
In a floating gate flash memory cell, the flash memory cell stores data by holding charge within the floating gate. In a write operation, charge can be placed on the floating gate through hot electron injection, or Fowler-Nordheim (F-N) tunneling. In addition, F-N tunneling can be typically used for erasing the flash memory cell through the removal of charge on the floating gate.
A common failure in flash memory is a programming failure due to an over-erasure of the flash memory. Prior Art FIG. 1A illustrates the over-erasure in a flash memory array 100A consisting of dual bit floating gate memory cells. For purposes of illustration only, in one case, the cross sectional view of the flash memory array 100A as presented in Prior Art FIG. 1A can be taken along line B–B′ of FIG. 3 in a dual bit case.
During multiple erase and program cycles, overerasure under the sidewall region 110 between a plurality of word lines 130 occurs. That is, over-erasure occurs due to hot hole injection of electrons into the sidewall region 110. For example, in an erase cycle of the conventional art, a negative voltage (e.g., −6 volts) is applied to an entire block of the array, a positive voltage (e.g., +6 volts) is applied to the drains of memory cells in the array, and the corresponding sources are left floating. As shown in Prior Art FIG. 1, the ONO layer 120 is erased during the erase process, as indicated by the darkened layer. This is because the potential of the sidewall region 110 reaches the applied potential on the plurality of word lines 130. As such, even the ONO layer 120 between each of the plurality of word lines 130 beneath the sidewall region 110 is erased.
During a program cycle, an isolated flash memory cell 130A in the array 100 is subjected to voltage to program the floating gate layer under the gate. Typically, a high positive voltage (e.g., +9.5 volts) is applied to the gate through an associated word line, the source is grounded, and a positive voltage (e.g., +5 volts) is applied to the drain through an associated bit line. Because the applied voltage is isolated to each of the gate, source, and drain regions of the programmed flash memory cell 130A, the programmed region, as shown in Prior Art FIG. 1 is isolated to the ONO layer under the gate.
After multiple erase and program cycles, because the programmed portion and erased portion do not overlap between the word lines 130, certain areas under the sidewall region 110 between the plurality of word lines 130 are subjected to multiple erase cycles without any correction from a program cycle. As a result this develops an accumulation of holes between the word lines 130 and under those sidewall regions subjected to multiple erase cycles. This reduces the threshold voltage of the associated flash memory cell and results in overerasure of those flash memory cells.
Correspondingly, prior Art FIG. 1B illustrates the over-erasure in a floating gate flash memory array 100B that consists of floating gate flash memory cells 140, to include flash memory cell 140A. For purposes of illustration only, in one case, the cross sectional view of the flash memory array 100B as presented in Prior Art FIG. 1B can be taken along line B–B′ of FIG. 3 in a floating gate case. Construction of each of the floating gate flash memory cells 140 in the floating gate flash memory array 100B includes, in part, a control gate 190, an ONO layer 180, a floating gate 170, and a tunnel oxide layer 160.
During multiple erase and program cycles, overerasure under the sidewall region 150 between a plurality of word lines that are coupled to the control gates 190 of each of the floating gate flash memory cells 140 occurs. That is, over-erasure occurs due to hole injection into the sidewall region 150.
Unfortunately, having an over-erased cell (floating gate or dual bit flash memory) on the same column line with a programmed cell can cause a failure when the programmed cell is read. The over-erased cell produces a leakage current and causes the entire column to malfunction. In particular, the current that is read from the column should be below a reference current (IRef) that corresponds to a properly configured threshold voltage, when reading a programmed cell. IRef is the erased cell reference current used for comparison.
However, if an over-erased cell is in the same column as that of the programmed cell, the over-erased cell has a threshold voltage that is less than 0 producing a leakage current (ILeak). As such, the total current read from the column will include the current from the programmed memory cell (IProgram) and the leakage current. If the sum of IProgram+ILeakage>IRef, then the total current being read from the column is greater than the reference current, and the programmed cell appears to be erased.
What is needed is a method for erasing flash memory cells that does not induce overerasure in an array of flash memory cells.